1. Field of the Invention
This invention relates to a high speed combination binary and decimal adder which is capable of performing binary and binary coded decimal addition with the same circuit.
2. Description of the Prior Art
In the prior art, a binary coded decimal addition usually requires a plurality of machine cycles because of the processing for the addition and subtraction of correction terms.
Generally, an adder is the nucleus of an arithmetic unit and is related to the data length, the numerical format used, etc. and the computation speed of the adder greatly affects the performance of the arithmetic unit. The numerical format is divided into a fixed-point representation and a floating-point representation, which are subdivided into binary and binary coded decimal representations, respectively.
A combination circuit which is inputted an augend X.sub.i, an addend Y.sub.i and a carry C.sub.i+1 and outputs a sum Z.sub.i and a carry C.sub.i is called a full adder. A circuit which obtains a sum and a carry from two inputs is a half adder.
By preparing the full adder for each digit and successively transferring the carry C.sub.i to higher order digits, a ripple carry adder is provided.
However, the ripple carry adder requires two logical stages for each digit and if the number of digits used is large, the operation time increases correspondingly. If wired logic is possible, one logical stage for each digit will do.
A carry look ahead adder simultaneously produces a carry at each digit and the carry at each digit is essentially determined by all of the bits of the lower order digits, and the fan-in variable increases rapidly.
A decimal number is represented by various methods such as BCD (Binary Coded Decimal), EXCESS 3, 2 out of 5, etc. but, in general, BCD is employed. In the BCD representation, each digit of a decimal number is represented by four bits and they are weighted with 8, 4, 2 and 1 and numerals 0 to 9 are represented as they are on the binary notation.
In general, binary and binary coded decimal adders are provided separately from each other and a binary coded decimal addition is performed by an operation using the binary adder three times.